Chip Gallery
LeoSoC GFMPW-1
An SoC with TRNGs
LeoSoC has been submitted to GFMPW-1
The SoC contains the following:
- Two RV32I cores running in parallel
- 32 word direct-mapped instruction cache for each core
- 4kB of shared memory
- SPI flash controller
- 2 UARTs
- 1 GPIO controller (24 I/Os)
- 15 different TRNGs
One Sprite Pony
SVGA sprite generator
One Sprite Pony has been submitted to Tiny Tapeout 05
- SVGA 800x600 60Hz output with 2 bits per color (internally reduced to 100x75)
- 40 MHz or 10 MHz operation depending on configuration
- Sprite with 12x12 pixels
- 4 different colors (6 bit rrggbb)
- 4 different backgrounds
- SPI Receiver
LeoSoC
A simple SoC
LeoSoC has been submitted to Efabless Open MPW-8
The SoC contains the following:
- 1 LeoRV32 Core (RV32I)
- 8 kB Work RAM
- 8 kB Video RAM (can also be used as Work RAM)
- SVGA Core (800 x 600, 40 MHz)
- UART (9600 baud)
- Blink (blink an LED)
Waveform Generator
My first chip
Waveform Generator has been submitted to Efabless Open MPW-7
A generic waveform generator divided into stimulus and driver units that can be arbitrarily interconnected.
Currently the following blocks are implemented:
Stimuli
- wfg_stim_sine
- wfg_stim_mem
Driver
- wfg_drive_spi
- wfg_drive_pat
Various
- wfg_interconnect
- wfg_core
- wfg_subcore