Bachelorthesis — Waveform Generator as ASIC
Introduction
I had the opportunity to work on a very interesting digital design for my bachelorthesis - and not only that - an important part of my work was to design an ASIC using the SkyWater Open Source PDK which targets the SKY130 process node.
All of this is possible thanks to a collaboration between Google and SkyWater Technology in 2020 to release and maintain the Process Design Kit for their 180nm-130nm hybrid technology as open source.
Google even went one step further and commissioned Efabless to manage the Open MPW Program. This program allows anyone to submit a design based on the Caravel Harness and - with a bit of luck depending on the available slots - have it manufactured for no cost. The only catch: The design must be completely open source :)
But designers are not on their own. OpenLane, based on OpenROAD, was developed specifically to work with the SkyWater PDK. OpenLane is a "no-human in the loop RTL to GDS compiler" that incorporates several components, all of which are open source.
Since then, 6 shuttles have already been sent to fabrication. The deadline for MPW-7 is September 12, and my design has already been submitted. But more about that later.
The git repositories for my work can be found here:
Waveform Generator
Together with semify I adapted the design and extended it with new features. The general idea is to have multiple stimuli and driver, each with its own function. The stimuli are connected with the driver via an interconnect. The interconnect can be configured, which means that any stimulus can be connected to any driver.
The first steps were to design the waveform generator and verify it. For simulation, I used cocotb as testbench environment with Icarus Verilog as underlying simulator. Once I was fairly confident with what I had, I moved on to FPGA prototyping.
For FPGA prototyping, I used the ULX3S, an awesome open source ECP5 dev board. The ECP5 series is well supported by the open source tools yosys and nextpnr, which I used to generate the bitstream.
This image shows the device utilization of the ECP5 LFE5U-85F (84K LUT). As you can see there is plenty of space for additional stimuli and driver in the future.
Caravel Harness
In order to submit the design to the Open MPW Program, it must be integrated with the Caravel Harness, which provides everything else for the chip to work so you can focus on your design.
The User Area is approximately 10mm² big. This is were the designs are placed. Enough space for a variety of applications.
Next, I had to create macros out of the waveform generator, which I could then place inside the User Area.
OpenLane
The git repositories from Efabless use OpenLane, the verification environment and the precheck as Docker containers. This has the advantage that there are no issues anymore with incompatible versions, as they plagued users in the beginning.
After I had everything set up, I ran the OpenLane flow with the waveform generator. This is the result.
What you can see here is a large grid with digital standard cells connected together. The size and density is configurable along with a lot of other parameters. As you can see, the upper right side has almost only decap cells, which are placeholders for when no functional cell is placed. But for me that's good enough because I'm not going to use up all the space anyway.
Still, some logic is required for the waveform generator to work. Most importantly SRAM for the memory stimuli. I decided to use two 2kB SRAM blocks and merge them together, since this was the largest size that came with the PDK. Larger sizes can be generated with OpenRAM. Then I needed a Wishbone peripheral to initialize the memory from the Caravel Harness side, and finally a Wishbone multiplexer to connect everything together.
Submission
Not really necessary for the submission - but I did it anyway - is the integration of the user design into the Caravel Harness. Afterwards the complete design looks like this:
A sight to behold :)
The final steps were uploading my design to Efabless Platform, running the MPW Precheck, and finally successfully completing the Tapeout job.
Can you spot my submission? ;)
- Here you can find all MPW-7 Projects.
- The MPW-7 Showcase gives detailed information about the projects.
Summary
All in all, I enjoyed working on the waveform generator. It was a lot of fun and very educational. I learned how to use OpenLane, how to integrate macros into a chip, and how to perform chip-level verification.
It's incredible how much is possible with open source tools, and it seems that it won't stop here. Already other foundries have released their PDKs as open source or are interested in doing so:
GlobalFoundries released the GF180MCU PDK as open source. Skywater Technologies is in the process of releasing the SKY90FD PDK as open source for their 90nm FDSOI process technology. And it seems like IHP Solutions is about to release their 130nm S13G2 PDK as open source, as announced at FSiC 2022.
The future looks promising for open source ASICs, and I'm very excited about what's to come in the near future!