GSoC23 — Final Project Report
The final project report for GSoC23 and my work on Icarus Verilog.
The final project report for GSoC23 and my work on Icarus Verilog.
Starting with the first timing check in Icarus Verilog! And also the last workweek blog post for GSoC23
Simulating a RISC-V CPU with interconnection delays!
Annotating interconnection delays of input/output vectors!
Taking a break from programming.
Finally a breakthrough!
Writing a test suite for interconnection delays and finding a hidden bug which has only now revealed itself.
Slow but steady progress towards annotating the interconnects.
It would be too good to be true if there were no problems.
A whole lot was going on this week. You better take a look inside.